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319942-02 december 2008 numonyx? strataflash ? embedded memory (j3-65nm) 256-mbit datasheet product features ? architecture ? multi-level cell technology: highest density at lowest cost ? 256 symmetrically-sized blocks of 128 kbytes ? performance ? 95 ns initial access time for easy bga ? 105 ns initial accsss time for tsop ? 25 ns 16-word asynchronous page-mode reads ? 512-word buffer programming at 1.46mbyte/s (typ) ? voltage and power ?v cc (core) = 2.7 v to 3.6 v ?v ccq (i/o) = 2.7 v to 3.6 v ? standby current: 65 a (typ) ? erase & program current: 35 ma (typ) ? page read: 12 ma (typ) ? quality and reliability ? operating temperature: -40 c to +85 c ? 100k minimum erase cycles per block ? 65 nm numonyx tm etox? x process technology ? security ? enhanced security options for code protection ? absolute protection with v pen = gnd ? individual block locking ? block erase/program lockout during power transition ? password access feature ? one-time programmable register: 64 otp bits, programmed with unique information by numonyx 64 otp bits, available for customer programming ? software ? 20 s (typ) program suspend ? 20 s (typ) erase suspend ? numonyx? flash data integrator (fdi) ? common flash interface (cfi) compatible ? packaging ?56-lead tsop ? 64-ball easy bga package
datasheet december 2008 2 319942-02 legal lines and disclaimers information in this document is provided in connection with numo nyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical co ntrol or safety systems, or in nuclear f acility applications. numonyx b.v. may make changes to specifications an d product descriptions at any time, without notice. numonyx b.v. may have patents or pending patent applications, tr ademarks, copyrights, or other intellectual property rights tha t relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implie d, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no respon sibility whatsoever for conf licts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to ob tain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting the numonyx website at http://www.numonyx.com . numonyx, the numonyx logo, and strataflash are trademarks or regist ered trademarks of numonyx b.v. or its subsidiaries in other countries. *other names and brands may be claimed as the property of others. copyright ? 2008, numonyx b.v., all rights reserved.
december 2008 datasheet 319942-02 3 numonyx? strataflash ? embedded memory (j3-65nm) contents 1.0 functional overview .................................................................................................. 5 1.1 document purpose .............................................................................................. 5 1.2 product overview................................................................................................. 5 1.3 configuration & memory map ................................................................................ 7 1.4 device id ........................................................................................................... 8 2.0 package information ................................................................................................. 9 2.1 56-lead tsop package, 256-mbit .......................................................................... 9 2.2 easy bga package, 256-mbit .............................................................................. 11 3.0 ballout ..................................................................................................................... 12 3.1 easy bga ballout, 256-mbit ................................................................................ 12 3.2 56-lead tsop package pinout, 256-mbit .............................................................. 13 4.0 signal descriptions .................................................................................................. 14 5.0 bus interface ........................................................................................................... 15 5.1 reads .............................................................................................................. 16 5.2 writes.............................................................................................................. 16 5.3 output disable .................................................................................................. 16 5.4 standby ........................................................................................................... 16 5.5 reset............................................................................................................... 17 6.0 command set .......................................................................................................... 18 6.1 device command codes ..................................................................................... 18 6.2 device command bus cycle................................................................................ 19 7.0 read operation ........................................................................................................ 21 7.1 read array ....................................................................................................... 21 7.2 asynchronous page mode read ........................................................................... 21 7.3 read status register ......................................................................................... 22 7.4 read device information .................................................................................... 22 7.5 cfi query ........................................................................................................ 22 8.0 program operation .................................................................................................. 24 8.1 single-word/byte programming .......................................................................... 24 8.2 buffered programming ....................................................................................... 24 8.3 suspend/resume .............................................................................................. 25 9.0 erase operation ....................................................................................................... 26 9.1 block erase ...................................................................................................... 26 9.2 suspend/resume .............................................................................................. 26 10.0 security ................................................................................................................... 28 10.1 normal block locking......................................................................................... 28 10.2 configurable block locking ................................................................................. 28 10.3 vpen protection ................................................................................................ 29 10.4 password access ............................................................................................... 29 11.0 registers ................................................................................................................. 30 11.1 status register ................................................................................................. 30 11.2 status signal .................................................................................................... 31 11.3 otp protection register...................................................................................... 32 12.0 power and reset specifications ............................................................................... 35 12.1 power-up and power-down................................................................................. 35
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 4 319942-02 12.2 reset specifications ...........................................................................................36 12.3 power supply decoupling....................................................................................37 13.0 maximum ratings an d operating conditions ............................................................38 13.1 absolute maximum ratings .................................................................................38 13.2 operating conditions..........................................................................................38 14.0 electrical characteristics ..........................................................................................39 14.1 dc current specifications ...................................................................................39 14.2 dc voltage specifications....................................................................................40 14.3 capacitance .....................................................................................................40 15.0 ac characteristics ....................................................................................................41 15.1 ac test conditions.............................................................................................41 15.2 ac read specifications .......................................................................................43 15.3 ac write specification ........................................................................................46 16.0 program and erase characteristics ...........................................................................48 16.1 program & erase specifications............................................................................48 17.0 ordering information ...............................................................................................49 a reference information .............................................................................................50 a.1 common flash interface .....................................................................................50 a.2 query structure output ......................................................................................50 a.3 flow charts.......................................................................................................57 b terms, definitions, and acronyms ............................................................................62 b.1 nomenclature....................................................................................................62 b.2 acronyms .........................................................................................................62 b.3 conventions......................................................................................................63 c revision history .......................................................................................................64
december 2008 datasheet 319942-02 5 numonyx? strataflash ? embedded memory (j3-65nm) 1.0 functional overview the numonyx? strataflash ? embedded memory (j3-65nm) provides improved mainstream performance with enhanced secu rity features, taking advantage of the high quality and reliability of the nor-based numonyx 65 nm etox? x process technology. offered in 32-mbit up through 256-mbit densities, the numonyx? embedded memory (j3-65nm) device brings reliable, low-vo ltage capability (3 v read, program, and erase) with high speed, low-power operation. the numonyx? strataflash ? embedded memory (j3-65nm) device is ideal for code and data applications where high density and low cost are required, such as in netw orking, telecommunications, digital set top boxes, audio recording, and digital imagin g. numonyx flash memory components also deliver a new generation of forward-compatible software support. by using the common flash interface (cfi) and scalable command set (scs), customers can take advantage of density upgrades and optimi zed write capabilities of future numonyx flash memory devices. 1.1 document purpose this document contains information pe rtaining to the numonyx? strataflash ? embedded memory (j3-65nm) device feat ures, operation, and specifications. the numonyx? embedded memory (j3-65nm) device is offered in single bit cell technology for 32-, 64-, 128-mbit densities. the numonyx? strataflash ? embedded memory (j3-65nm) device is offered in multi-level cell technology for 256-mbit density. this document just covers 256-mbit die information. unless otherwise indicated throughout the rest of this document, numonyx? strataflash ? embedded memory (j3-65nm) is referred to as j3-65nm . 1.2 product overview the 256-mbit j3-65nm is organized as 256 individual 128kbyte symmetrical blocks. a 128-bit protection register has multiple uses, including unique flash device identification. the j3-65nm device includes new security features that were not available on the (previous) 0.25m, 0.18m, and 0.13m vers ions of the j3 family. the new security features can be implemented to protect critical code and data from unwanted modification (program or erase). usage can be defined to fit the specific needs of each customer. the j3-65nm optimized architecture and interf ace dramatically increases read performance by supporting page-mode reads. this read mode is ideal for non-clock memory systems. the j3-65nm common flash interface (cfi) permits software algorithms to be used for entire families of devices. this allows de vice-independent, jedec id-independent, and forward- and backward-compatible software support for the specified flash device families. flash vendors can standardize th eir existing interfaces for long-term compatibility. the scalable command set (scs) allows a sing le, simple software driver in all host systems to work with all scs-compliant flas h memory devices, independent of system- level packaging (e.g., memory card, simm, or direct-to-board placement). additionally, scs provides the highest syst em/device data transfer rates and minimizes device and system-level implementation costs.
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 6 319942-02 a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a va lid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. a block erase operation erases one of the devi ce?s 128-kbyte blocks typically within one second, independent of other blocks. each block can be independently erased 100,000 times. block erase suspend mode allows system software to suspend block erase to read or program data from any other block. similarly, program suspend allows system software to suspend programming (byte/word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. each device incorporates a write buffer of 512 words to allow optimum programming performance. by using the write buffer data is programmed more efficiently in buffer increments. memory blocks are selectively and individua lly lockable in-system. individual block locking uses block lock-bits to lock and unlock blocks. block lock-bits gate block erase and program operations. lock-bit configuratio n operations set and clear lock-bits (using the set block lock-bit and clear block lock-bits commands). the status register indicates when the wsm?s block erase, program, or lock-bit configuration operation completes. the sts (status) output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus softwa re polling) and status masking (interrupt masking for background block erase, for example). status indication using sts minimizes both cpu overhead and system power consumption. when configured in level mode (default mode), it acts as a ry/b y# signal. when low, sts indicates that the wsm is performing a block erase, program, or lock-bit configuration. sts-high indicates that the wsm is ready for a new command, block erase is suspended (and programming is inactive), prog ram is suspended, or the device is in reset/power-down mode. additionally, the configuration command allows the sts signal to be configured to pulse on completion of programming and/or block erases. three ce signals are used to enable and disable the device. a unique ce logic design ( see table 6, ?chip enable truth table for 256-mb? on page 15 ) reduces decoder logic typically required for multi-chip designs. exte rnal logic is not required when designing a single chip, a dual chip, or a 4-chip miniature card or simm module. the byte# signal allows either x8 or x16 read/writes to the device: ? byte#-low enables 8-bit mode; address a0 selects between the low byte and high byte. ? byte#-high enables 16-bit operation; address a1 becomes the lowest order address and address a0 is not used (don?t care). when the device is disabled (see table 6, ?chip enable truth table for 256-mb? on page 15 ), with cex at v ih and rp# at v ih , the standby mode is enabled. when rp# is at v il , a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (t phqv ) is required from rp# going high until data outputs are valid. likewise, the device has a wake time (t phwl ) from rp#-high until writes to the cui are recognized. with rp# at v il , the wsm is reset and the status register is cleared.
december 2008 datasheet 319942-02 7 numonyx? strataflash ? embedded memory (j3-65nm) 1.3 configuration & memory map the j3-65nm device features a symmetrically-blocked architecture. the flash device main array is divided as follows: ? 256-mbit, organized into two-hundred-fifty-six 128-kbyte blocks. figure 1: j3-65nm memory map 64-kword block 64-kword block 64-kword block word wide (x16) mode 7fffff 7 f0000 01ffff 010000 00ffff 000000 128-kbyte block 128-kbyte block 128-kbyte block byte-wide (x8) mode 0ffffff 0fe0000 003 ffff 0020000 001 ffff 0000000 a<24:0> 256 mbit 64-kword block 3fffff 3 f0000 128-kbyte block 07fffff 07 e0000 1 0 127 63 1 0 127 63 64-kword block 128-kbyte block ffffff ff0000 1ffffff 1fe 0000 255 255 256- mbit a<24:1> 256 mbit
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 8 319942-02 1.4 device id table 1: device identifier codes code address data device code 256-mbit 00001h 001dh
december 2008 datasheet 319942-02 9 numonyx? strataflash ? embedded memory (j3-65nm) 2.0 package information 2.1 56-lead tsop package, 256-mbit notes: 1. one dimple on package denotes pin 1. 2. if two dimples, then the larger dimple denotes pin 1. 3. pin 1 will always be in the upper left corner of the package, in refere nce to the product mark. figure 2: 56-lead tsop package mechanical a 0 l detail a y d c z pin 1 e d 1 b detail b see detail a e see detail b a 1 seating plane a 2 see note 2 see notes 1 and 3 table 2: 56-lead tsop dimension table parameter symbol millimeters inches min nom max min nom max package height a 1.200 0.047 standoff a 1 0.050 0.002 package body thickness a 2 0.965 0.995 1.025 0.038 0.039 0.040 lead width b 0.100 0. 150 0.200 0.004 0.006 0.008 lead thickness c 0.100 0.150 0.200 0.004 0.006 0.008 package body length d 1 18.200 18.400 18.600 0.717 0.724 0.732 package body width e 13.800 14.000 14.200 0.543 0.551 0.559 lead pitch e 0.500 0.0197
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 10 319942-02 terminal dimension d 19.80 0 20.00 20.200 0.780 0.787 0.795 lead tip length l 0.500 0.600 0.700 0.020 0.024 0.028 lead count n 56 56 lead tip angle 0 3 5 0 3 5 seating plane coplanarity y 0.100 0.004 lead to package offset z 0.150 0.250 0.350 0.006 0.010 0.014 table 2: 56-lead tsop dimension table parameter symbol millimeters inches min nom max min nom max
december 2008 datasheet 319942-02 11 numonyx? strataflash ? embedded memory (j3-65nm) 2.2 easy bga package, 256-mbit figure 3: easy bga mechanical specifications table 3: easy bga pack age dimensions table parameter symbol millimeters inches min nom max min nom max package height (256 mbit) a 1.200 0.0472 ball height a1 0.250 0.0098 package body thickne ss (256 mbit) a2 0.780 0.0307 ball (lead) width b 0.330 0.430 0.530 0.0130 0.0169 0.0209 package body width d 9.900 10.000 10.100 0.3898 0.3937 0.3976 package body length e 12. 900 13.000 13.100 0.5079 0.5118 0.5157 pitch e 1.000 0.0394 ball (lead) count n 64 64 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along d (256 mb) s1 1.400 1.500 1.600 0.0551 0.0591 0.0630 corner to ball a1 distance along e (256 mb) s2 2.900 3.000 3.100 0.1142 0.1181 0.1220 2 ball a1 corner 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 e a b c d e f g h seating plane s 1 s e b top view - plastic backside complete ink mark not shown bottom view - ball side up y a a1 d a b c d e f g h ball a1 corner a2
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 12 319942-02 3.0 ballout j3-65nm is available in two package types. all densities of the j3-65nm devices are supported on both 64-ball easy bga and 56 -lead thin small outline package (tsop) packages. the figures below show the ballouts. 3.1 easy bga ballout figure 4: easy bga ballout a1 a6 a8 vpen a13 vcc a18 a22 a2 vss a9 ce0 a14 rfu a19 ce1 a3 a7 a10 a12 a15 rfu a20 a21 a4 a5 a11 rp# rfu rfu a16 a17 dq8 dq1 dq9 dq3 dq4 rfu dq15 sts byte# dq0 dq10 dq11 dq12 rfu rfu oe# a23 a0 dq2 vccq dq5 dq6 dq14 we# ce2 rfu vcc vss dq13 vss dq7 a24 12345678 a b c d e f g h easy bga top view ? ball side down a22 ce1 a21 a17 sts oe # we# a24 8 a18 a19 a20 a16 dq15 rfu dq14 dq7 7 vcc rfu rfu rfu rfu rfu dq6 vss 6 a13 a14 a15 rfu dq4 dq12 dq5 dq13 5 vpen ce0 a12 rp# dq3 dq11 vccq vss 4 a8 a9 a10 a11 dq9 dq10 dq2 vcc 3 a6 vss a7 a5 dq1 dq0 a0 rfu 2 a1 a2 a3 a4 dq8 byte# a23 ce2 1 a b c d e f g h easy bga bottom view ? ball side up
december 2008 datasheet 319942-02 13 numonyx? strataflash ? embedded memory (j3-65nm) 3.2 56-lead tsop package pinout, 256-mbit notes: 1. no internal connection on pin 9; it may be driven or floated. for legacy designs, pin can be tied to vcc. figure 5: 56-lead tsop package pinout (256 mbit) 56-lead tsop standard pinout 14 mm x 20 mm top view 1 3 4 2 5 7 8 6 9 11 12 10 13 15 16 14 17 19 20 18 21 23 24 22 25 27 28 26 56 54 53 55 52 50 49 51 48 46 45 47 44 42 41 43 40 38 37 39 36 34 33 35 32 30 29 31 a 22 a 21 a 20 ce 1 a 19 a 17 a 16 a 18 a 14 a 13 a 15 a 12 v pen rp# ce 0 a 11 a 9 a 8 a 10 gnd a 6 a 5 a 7 a 4 a 2 a 1 a 3 a 24 oe# sts we# dq 15 dq 14 dq 6 dq 7 gn d dq 5 dq 12 dq 13 dq 4 gnd dq 11 v ccq dq 3 dq 2 v cc dq 10 dq 9 dq 8 dq 0 dq 1 a 0 a 23 ce 2 byt e v cc (1)
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 14 319942-02 4.0 signal descriptions ta b l e 4 lists the active signals used on j3-65nm and provides a description of each. table 4: tsop & easy bga signal descriptions symbol type name and function a0 input byte-select address: selects between high and low byte when the device is in x8 mode. this address is latched during a x8 program cycle. not used in x16 mode (i.e., the a0 input buffer is turned off when byte# is high). a[max:1] input address inputs: inputs for addresses during read and program operations. addresses are internally latched during a program cycle: 256-mbit ? a[24:1] dq[7:0] input/ output low-byte data bus: inputs data during buffer writes and programming, and inputs commands during cui writes. outputs array, cfi, identifier, or status data in the appropriate read mode. data is internally latched during write operations. dq[15:8] input/ output high-byte data bus: inputs data during x16 buffer writes and programming operations. outputs array, cfi, or identifier data in the appropriate read mode; not used for status register reads. data is internally latched during write op erations in x16 mode. dq [15:8] float in x8 mode ce[2:0] input chip enable: activate the 256-mbit devices? control lo gic, input buffers, decoders, and sense amplifiers. when the device is de-selected (see table 6, ?chip enable truth table for 256-mb? on page 15 ), power reduces to standby levels. all timing specifications are the same for these three signals. device selection occurs with the falling edge of ce0, ce1, or ce2 that enables the device. device deselection occurs with the rising edge of ce0, ce1, or ce2 that disables the device (see table 6, ?chip enable truth table for 256-mb? on page 15 ). rp# input reset: rp#-low resets internal automation and puts the device in power-down mode. rp#-high enables normal operation. exit from reset sets th e device to read array mode. when driven low, rp# inhibits write operations which provides data protection during power transitions. oe# input output enable: activates the device?s outputs through the data buffers during a read cycle. oe# is active low. we# input write enable: controls writes to the cui, the write bu ffer, and array blocks. we# is active low. addresses and data are latched on the rising edge of we#. sts open drain output status: indicates the status of the internal stat e machine. when config ured in level mode (default), it acts as a ry/by# signal. when config ured in one of its pulse modes, it can pulse to indicate program and/or erase completion. for altern ate configurations of the status signal, see the configurations command and section 11.2, ?status signal? on page 31 . sts is to be tied to vccq with a pull-up resistor. byte# input byte enable: byte#-low places the device in x8 mode; da ta is input or output on dq[7:0], while dq[15:8] is placed in high-z. address a0 selects between the high and low byte. byte#-high places the device in x16 mode, and turns off the a0 input buffer. address a1 becomes the lowest- order address bit. vpen input erase / program / block lock enable: for erasing array blocks, programming data, or configuring lock-bits. with v pen v penlk , memory contents cannot be altered. vcc power core power supply: core (logic) source voltage. writes to the flash array are inhibited when v cc v lko . caution: device operation at invalid vcc voltages should not be attempted. vccq power i/o power supply: power supply for input/output buffers .this ball can be tied directly to v cc . gnd/vss supply ground: ground reference for device logic voltages. connect to system ground. nc ? no connect: lead is not interna lly connected; it may be driven or floated. rfu ? reserved for future use: balls designated as rfu are reserved by numonyx for future device functionality and enhancement .
december 2008 datasheet 319942-02 15 numonyx? strataflash ? embedded memory (j3-65nm) 5.0 bus interface this section provides an overview of bus operations. there are three operations flash memory: read, program (write), and erase. ce[2:0]-enable, oe#-low, we#-high and rp #-high enable device read operations. addresses are always assumed to be valid. oe#-low activates the outputs and gates selected data onto the i/o bus. we#-low enables device write operations. ta b l e 5 summarizes the necessary states of each control signal for different modes of operations. ce0, ce1 and ce2 control device acti vation. with the proper input (see figure 6, ?chip enable truth table for 256-mb ) the device gets selected, which in turn activates its internal circuits. we# and oe# determine the direction of the data buffers (input or output). table 5: bus operations mode rp# ce x (1) oe# (2) we# (2) dq 15:0 (3) sts (default mode) v pen notes reads: async., status, query and identifier v ih enabled v il v ih d out high-z x 4,6 output disable v ih v ih enabled v ih high-z high-z x command writes v ih enabled v ih v il d in high z x 6,7 array writes (8) v ih enabled v ih v il d in v il v penh 8,5 standby v ih disabled x x high z high z x reset/power-down v il x x x high z high z x notes: 1. see ta b l e 6 for valid ce x configurations. 2. oe# and we# should never be asserted simultaneously. if done so, oe# overrides we#. 3. dq refers to dq[7:0] when byte# is low and dq[15:0] if byte# is high. 4. refer to dc characteristics. when v pen v penlk , memory contents can be read but not altered. 5. x should be v il or v ih for the control pins and v penlk or v penh for v pen . for outputs, x should be v ol or v oh . 6. in default mode, sts is v ol when the wsm is executing internal block er ase, program, or a lo ck-bit configuration algorithm. it is v oh (pulled up by an extern al pull up resistance 10k) when the wsm is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset power-down mode. 7. see ta b l e 7 for valid din (user commands) during a write operation 8. array writes are either program or erase operations. table 6: chip enable truth table for 256-mb ce2 ce1 ce0 device v il v il v il enabled v il v il v ih disabled v il v ih v il disabled v il v ih v ih disabled v ih v il v il enabled v ih v il v ih enabled v ih v ih v il enabled v ih v ih v ih disabled note: for single-chip applications, ce2 and ce1 can be connected to gnd.
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 16 319942-02 5.1 reads reading from flash memory outputs stored information to the processor or chipset, and does not change any contents. reading ca n be performed an unlimited number of times. besides array data, other types of data such as device information or device status are available from the flash. to perform a bus read operation, cex (refer to table 6 on page 15 ) and oe# must be asserted. cex is the device-select control; when active, it enables the flash memory device. oe# is the data-output control; when active, the addressed flash memory data is driven onto the i/o bus. for all read states, we# and rp# must be de-asserted. see section 7.0, ?read operation? on page 21 . 5.2 writes writing or programming to the device is wher e the host writes information or data into the flash device for non-volatile storage. wh en the flash device is programmed, ?ones? are changed to ?zeros?. ?zeros? cannot be programmed back to ?ones?. to do so, an erase operation must be performed. writing commands to the command user interface (cui) enables various modes of operat ion, including the following: ? reading of array data ? common flash interface (cfi) data ? identifier codes, inspection, and clearing of the status register ? block erasure, program, and lock-bit configuration (when v pen = v penh ) erasing is performed on a block basis ? all flash cells within a block are erased together. any information or data previously stored in the block will be lost. erasing is typically done prior to programming. the block er ase command requires appropriate command data and an address within the block to be erased. the byte/word program command requires the command and address of the loca tion to be written. set block lock-bit commands require the command and block within the device to be locked. the clear block lock-bits command requires the command and address within the device to be cleared. the cui does not occupy an addressable memory location. it is written when the device is enabled and we# is active . the address and data needed to execute a command are latched on the rising edge of we# or the firs t edge of ce0, ce1, or ce2 that disables the device (see table 6 on page 15 ). standard microprocessor write timings are used. 5.3 output disable with cex asserted, and oe# at a logic-high level (v ih ), the device outputs are disabled. output signals d[15:0] are placed in a high-impedance state. 5.4 standby ce0, ce1, and ce2 can disable the device (see table 6 on page 15 ) and place it in standby mode. this manipulation of cex substantially reduces device power consumption. d[15:0] outputs are placed in a high-impedance state independent of oe#. if deselected during block erase, pr ogram, or lock-bit configuration, the wsm continues functioning, and consuming active power until the operation completes.
december 2008 datasheet 319942-02 17 numonyx? strataflash ? embedded memory (j3-65nm) 5.5 reset rp# at v il initiates the reset/power-down mode. in read modes, rp#-low deselects the memory, places output drivers in a high- impedance state, and turns off numerous internal circuits. rp# must be held low for a minimum of t plph . time t phqv is required after return from reset mode until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui is reset to read array mode and status register is set to 0080h. during block erase, program, or lock-bit configuration modes, rp#-low will abort the operation. in default mode, sts transitions low and remains low for a maximum time of t plph + t phrh until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. time t phwl is required after rp# goes to logic-high (v ih ) before another command can be written. as with any automated device, it is importan t to assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. if a cpu reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. numonyx flash memories allow proper initialization following a system reset through the use of th e rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu.
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 18 319942-02 6.0 command set 6.1 device command codes the system central processing unit provides control of all in-system read, write, and erase operations of the device via the system bus. the on-chip wsm manages all block- erase and program algorithms. device commands are written to the cui to control all flash memory device operations. the cui does not occupy an addressable memory location; it is the mechanism through which the flash device is controlled. ta b l e 7 shows valid device command codes and descriptions. table 7: command codes and definitions (sheet 1 of 2) mode code device mode description read 0xff read array places the device in read ar ray mode. array data is output on dq[15:0]. 0x70 read status register places the device in read status register mode. the device enters this mode after a program or erase command is issued. sr data is output on dq[7:0]. 0x90 read device id or configuration register places device in read device iden tifier mode. subsequent reads output manufacturer/device codes, configuration register data, block lock status, or otp register data on dq[15:0]. 0x98 read query places the device in read query mode. subsequent reads output common flash interface information on dq[7:0]. 0x50 clear status register the wsm can only set sr error bits. the clear status register command is used to clear the sr error bits. program 0x40 word/byte program setup first cycle of a 2-cycle programming command , prepares the cui for a write operation. on the next write cycle, the address and data are latched and the wsm executes the programming algorithm at the addressed location. during program operations, the device responds only to read status register and program suspend commands. ce x or oe# must be toggled to update the status register in asynchronous read. ce x must be toggled to update the sr data for synchronous non-array reads. the read array command must be issued to read array data after programming has finished. 0xe8 buffered program this command loads a variable number of words up to the buffer size of 512 words onto the program buffer in x16 mode. (1) 0xd0 program confirm the confirm command is issued after the da ta streaming for writing into the buffer is done. this instru cts the wsm to perform the buffe red program algorithm, writing the data from the buffer to the flash memory array. erase 0x20 block erase setup first cycle of a 2-cycle command; prepares the cui for a block-erase operation. the wsm performs the erase algorithm on the block addressed by the erase confirm command. if the next command is not the erase confirm (0 xd0) command, the cui sets status register bits sr [5,4], and pl aces the device in read status register mode. 0xd0 block erase confirm if the first command was block erase setup (0x20), the cui latches the address and data, and the wsm erases the addressed block. during block-erase operations, the device responds only to read status register and erase suspend commands. ce x or oe# must be toggled to update the status register in asynchronous read. ce x must be toggled to update the sr data for synchronous non-array reads. suspend 0xb0 program or erase suspend this command issued to any device address initiates a suspend of the currently- executing program or block erase operation. the status register indicates successful suspend operation by setting either sr.2 (program suspended) or sr 6 (erase suspended), along with sr.7 (ready). the wsm remains in the suspend mode regardless of control signal states (except for rprp# asserted). 0xd0 suspend resume this command issued to any device address resumes the suspended program or block-erase operation.
december 2008 datasheet 319942-02 19 numonyx? strataflash ? embedded memory (j3-65nm) 6.2 device command bus cycle device operations are initiated by writing specific device commands to the cui. see table 8, ?command bus cycles? on page 19 . several commands are used to modify array data including word program and block erase commands. writing either command to the cui initiates a sequence of internally - timed functions that culminate in the completion of the requested task. howeve r, the operation can be aborted by either asserting rp# or by issuing an appropriate suspend command. protection 0x60 block lock setup first cycle of a 2-cycle command; prepares the cui for block lock configuration changes. if the next command is not block lock (0x01), block unlock (0xd0), the cui sets sr.5 and sr.4, indicating a command sequence error. 0x01 block lock if the previous command was block lock setup (0x60), the addressed block is locked. 0xd0 unlock block if the previous command was block lock setup (0x60), on issuing this command, all of the block lock bits that are set are cleared in parallel. 0xc0 protection program setup first cycle of a 2-cycle command; prepares the device for a otp register or lock register program operation. the second cycle latches the register address and data, and starts the programming algorithm to program data the otp array. 0xeb extended function interface (efi) this command is used in security features . first cycle of a multiple-cycle command second cycle is a sub-op-code, the data written on third cycle is one less than the word count; the allowable value on this cycle are 0 through 511. the subsequent cycles load data words into the program buffer at a specified address until word count is achieved. for additional information and collateral request, please contact your filed. sts configuration b8h configuration set-up configures the sts pin to different states. the default operation of the sts pin is the level mode, just like ry/by# which in dicates if the write state machine is busy or available. using this command the st s pin can be configured to generate an erase/program interrupt pulse once the operation is done. 00h configuration code configures the sts pin in level mode. makes the sts pin function like a ry/by# pin. 01h configures the sts pin to generate a pulse once an erase operation is completed. 02h the sts pin is configured to generate a pulse once a program operation completes. 03h the sts pin is configured to generate a pulse when either a program or erase operation completes. table 7: command codes and de finitions (sheet 2 of 2) mode code device mode description table 8: command bus cycles (sheet 1 of 2) mode command bus cycles first bus cycle second bus cycle last bus cycle addr (1) data (2) addr (1) data (2) addr (1) data (2) read read array 1 dna 0xff --- --- --- --- read status register 2 dna 0x70 dna srd --- --- read device identifier 2 dna 0x90 dba + ia id --- --- read cfi 2 dna 0x98 dba + cfi-a cfi-d --- --- clear status register 1 dna 0x50 --- --- --- --- program word program 2 wa 0x40 wa wd --- --- buffered program (3) > 2 wa 0xe8 wa n - 1 wa 0xd0
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 20 319942-02 erase block erase 2 ba 0x20 ba 0xd0 --- --- suspend program/erase suspend 1 dna 0xb0 --- --- --- --- program/erase resume 1 dna 0xd0 --- --- --- --- protection lock block 2 ba 0x60 ba 0x01 --- --- unlock block 2 ba 0x60 ba 0xd0 --- --- program otp register 2 otp-ra 0xc0 otp-ra otp-d --- --- program lock register 2 lra 0xc0 lra lrd --- --- sts configuration 2 ba 0xb8 ba register data --- --- extended flash interface (4) > 2 wa 0xeb wa sub-op code wa 0xd0 notes: 1. first command cycle address should be the same as the operation?s target address. dba = device base address dna = address within the device. ia = identification code address offset. cfi-a = read cfi address offset. wa = word address of memory location to be written. ba = address within the block. otp-ra = otp register address. lra = lock register address. rcd = read configuration register data on a[15:0]. 2. id = identifier data. cfi-d = cfi data on dq[15:0]. srd = status register data. wd = word data. n = word count of data to be loaded into the write buffer. otp-d = otp register data. lrd = lock register data. 3. the second cycle of the buffered program command is the word count of the data to be loaded into the write buffer. this is followed by up to 512 wo rds of data.then the confirm command (0xd0) is issued, triggering the ar ray programming operation. 4. the second cycle is a sub-op-code, the data written on third cycle is n-1; 1= december 2008 datasheet 319942-02 21 numonyx? strataflash ? embedded memory (j3-65nm) 7.0 read operation the device can be in any of four read states: read array, read identifier, read status register or read query. upon power-up, or after a reset, the devi ce defaults to read array mode. to change the read state, the appropriate read command must be written to the device (see section 6.1, ?device command codes? on page 18 ). the following sections describe read-mode operations in detail. 7.1 read array upon power-up or return from reset, the device defaults to read array mode. issuing the read array command places the device in read array mode. subsequent reads output array data on dq[15:0]. the device remains in read array mode until a different read command is issued, or a program or erase operation is performed, in which case, the read mode is auto matically changed to read status. to change the device to read array mode while it is programming or erasing, first issue the suspend command. after the operation has been suspended, issue the read array command. when the program or erase operation is subsequently resumed, the device will automatically revert back to read status mode. note: issuing the read array command to the device while it is actively programming or erasing causes subsequent reads from the device to output invalid data. valid array data is output only after the prog ram or erase operation has finished. the read array command functions independent of the voltage level on vpen. 7.2 asynchronous page mode read j3-65nm supports asynchronous page mode read access only. j3-65nm also supports byte or word accesses depending on the level of byte#. ? if byte# is at v il then the data will be outputted on the dq 7-0 . this read access is called ?x8 mode?. the dq 15-8 signals will be in high-z. ?if byte# is at v ih then the data will be outputted on dq 15-0 .this read access is called ?x16 mode.? the default read mode of the device after power up or hardware reset is read array mode.the read array/ software reset co mmand returns the device to read array mode. any following read accesses to devices returns main array data. the page size is sixteen words (32 bytes). each read operation internally retrieves sixteen words of data, which are determined by addressed bits a[max:5].in x16 mode, the first word of data, defined by a[4:1], is output to the data bus within t avqv . after this initial access time, subsequent words can be output to the data bus by changing address bits a[4:1]. in x8 mode, the first byte of data, defined by a[4:0], is output to the data bus within t avqv . after this initial access time, subsequent bytes can be output to the data bus by changing address bits a[4:0]. any subsequent data word(s) within the page can be output to the data bus within t apa , which is much shorter than t avqv . the internal read operation can also be initiated by asserting ce x while addresses are valid or changing the a[max:5] while ce x is asserted.
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 22 319942-02 7.3 read status register issuing the read status register command places the device in read status register mode. subsequent reads output status regi ster information on dq[7:0], and 00h on dq[15:8]. the device remains in read status register mode until a different read- mode command is issued. performing a program, erase, or block-lock operation also changes the device?s read mode to read status register mode. the status register is updated on the falling edge of ce, or oe# when ce is active. status register contents are valid only when sr.7 = 1. when wsm is busy, sr.7 indicates the wsm?s state and sr[6:0] are in high-z state. the read status register command functions independent of the voltage level on vpen. 7.4 read device information issuing the read device information command places the device in read device information mode. subsequent reads output device information on dq[15:0]. the device remains in read device informat ion mode until a different read command is issued. also, performing a program, erase, or block-lock operation changes the device to read status register mode. the read device information command functi ons independent of the voltage level on vpen. 7.5 cfi query the cfi query table contains an assortment of flash product information such as block size, density, allowable command sets, electrical specifications, and other product information. the data contained in this table conforms to the cfi protocol. table 9: device identifier information item address (1,2,3) data manufacturer code 0x00 0x89h device id code 0x01 id (see ta b l e 1 ) block lock configuration: bba + 0x02 lock bit: ? block is unlocked dq0 = 0b0 ? block is locked dq0 = 0b1 j3a block lock compatibility 0x03 0x000 (4) general purpose register (5) dba + 0x07 general data lock register 0 0x80 pr-lk0 64-bit factory-programmed otp register 0x81?0x84 factory otp register data 64-bit user-programmable otp register 0x85?0x88 user otp register data notes: 1. bba = block base address. 2. dba = device base address, numonyx reserves other configuration address locations 3. a 0 is not used in either x8 or x16 modes during manufacturer and device id reads. the lowest order address line is a 1 . 4. when reading block base address + 00003h, the user needs to read 0000h to be backward compatibly to j3a. 5. the gpr is used as read out register for extended functional interface (efi) command.
december 2008 datasheet 319942-02 23 numonyx? strataflash ? embedded memory (j3-65nm) issuing the cfi query command places the device in cfi query mode. subsequent reads output cfi information on dq[15:0]. the device remains in cfi query mode until a different read command is issued, or a program or erase operation is performed, which changes the read mode to read status register mode. the cfi query command functions independent of the voltage level on vpen.
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 24 319942-02 8.0 program operation all programming operations require the addressed block to be unlocked, and a valid vpen voltage applied throughout the programming operation. otherwise, the programming operation will abor t, setting the appropriate status register error bit(s). the following sections describe each programming method. 8.1 single-word/byte programming array programming is performed by firs t issuing the single-word/byte program command. this is followed by writing the desi red data at the desired array address. the read mode of the device is automatically changed to read status register mode, which remains in effect until another read-mode command is issued. during programming, sts and the status register indicate a busy status (sr.7 = 0). upon completion, sts and the status register indicate a ready status (sr.7 = 1). the status register should be checked for any errors (sr.4), then cleared. note: issuing the read array command to the device while it is actively programming causes subsequent reads from the device to output invalid data. valid array data is output only after the program operation has finished. standby power levels are not realized unt il the programming operation has finished. also, asserting rp# aborts the programming operation, and array contents at the addressed location are indeterminate. the addressed block should be erased, and the data re-programmed. if a single-word/ byte program is attempted when the corresponding block lock-bit is set, sr.1 and sr.4 will be set. 8.2 buffered programming the device features a 512-word buffer to enable optimum programming performance. for buffered programming, data is first written to an on-chip write buffer. then the buffer data is programmed into the flash memory array in buffer-size increments. this can improve system programming perfor mance significantly over non-buffered programming. (see figure 19, ?buffer program flowchart? on page 59 ). when the buffered programming setup command is issued, status register information is updated and reflects the availability of the buffer. sr.7 indicates buffer availability: if set, the buffer is available; if cleared, the buffer is not available. to retry, issue the buffered programming setup command again, and re-check sr.7. when sr.7 is set, the buffer is ready for loading. on the next write, a word count is written to the device at the buffer address. this tells the device how many data words will be wri tten to the buffer, up to the maximum size of the buffer. on the next write, a device start address is given along with the first data to be written to the flash memory array. subsequent writ es provide additional device addresses and data. all data addresses must lie within the start address plus the word count. optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 512-word boundary (a[9:1] = 0x00). the maximum buffer size would be 256-word if the misaligned address range is crossing a 512-word boundary during programming. after the last data is written to the buff er, the buffered programming confirm command must be issued to the original block address. the wsm begins to program buffer contents to the flash memory array. if a command other than the buffered
december 2008 datasheet 319942-02 25 numonyx? strataflash ? embedded memory (j3-65nm) programming confirm command is written to the device, a command sequence error occurs and sr[7,5,4] are set. if an error o ccurs while writing to the array, the device stops programming, and sr[7,4] are set, indicating a programming failure. when buffered programming has completed, additional buffer writes can be initiated by issuing another buffered programming se tup command and repeating the buffered program sequence. if an attempt is made to program past an erase-block boundary using the buffered program command, the device aborts the operation. this generates a command sequence error, and sr[5,4] are set. if buffered programming is attempted while vpen is below v penlk , sr[4,3] are set. if any errors are detected that have set status register bits, the status register should be cleared using the clear status register command. note: in x8 mode, a maximum of 256 bytes of data can be loaded into the write buffer as n can have a max value of ffh. 8.3 suspend/resume an erase or programming operation can be suspended to perform other operations, and then subsequently resumed. please refer to chapter 9.0, ?suspend/resume? for details.
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 26 319942-02 9.0 erase operation flash erasing is performed on a block basis. an entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. when a block is erased, all bits within that block read as logical ones. the following sections describe block erase operations in detail. 9.1 block erase erasing a block changes ?zeros? to ?ones?. to change ones to zeros, a program operation must be performed ( see section 8.0, ?program operation? ). erasing is performed on a block basis - an entire block is erased each time an erase command sequence is issued. once a block is fully erased, all addressable locations within that block read as logical ones (ffffh). only one block-erase operation can occur at a time, and is not permitted during a program suspend (see figure 21, ?block erase flowchart? on page 61 ). note: a block-erase operation requires the addressed block to be unlocked, and a valid voltage applied to vpen throughout the block-erase operation. otherwise, the operation will abort, setting the appropriate status register error bit(s). the erase confirm command latches the ad dress of the block to be erased. the addressed block is preconditioned (programmed to all zeros), erased, and then verified. the read mode of the device is automatica lly changed to read status register mode, and remains in effect until another read-mode command is issued. during a block-erase operation, sts and the status register indicates a busy status (sr.7 = 0). upon completion, sts and the st atus register indicates a ready status (sr.7 = 1). the status register should be ch ecked for any errors, then cleared. if any errors did occur, subsequent erase commands to the device are ignored unless the status register is cleared. the only valid commands during a block erase operation are read status and erase suspend. after the block-erase operation has completed, any valid command can be issued. note: issuing the read array command to the device while it is actively erasing causes subsequent reads from the device to output invalid data. valid array data is output only after the block-erase operation has finished. standby power levels are not realized until the block-erase operation has finished. also, asserting rp# aborts the block-erase operat ion, and array contents at the addressed location are indeterminate. the addressed block should be erased before programming within the block is attempted. 9.2 suspend/resume an erase or programming operation can be suspended to perform other operations, and then subsequently resumed. ta b l e 8 shows the suspend and resume command bus- cycles (see figure 18, ?program/erase suspend/resume flowchart? on page 57 ). note: all erase and programming operations require the addressed block to remain unlocked with a valid voltage applied to vpen throug hout the suspend operation. otherwise, the block-erase or programming operation will abort, setting the appropriate status register error bit(s). also, asserting rp# aborts suspended block-erase and programming operations, rendering array contents at the addressed location(s) indeterminate.
december 2008 datasheet 319942-02 27 numonyx? strataflash ? embedded memory (j3-65nm) to suspend an on-going erase or program operation, issue the suspend command to any device address. the program or erase op eration suspends at pre-determined points during the operation after a delay of t susp . suspend is achieved when sts (in ry/by# mode) goes high, sr[7,6] = 1 (erase-suspend) or sr[7,2] = 1 (program-suspend). note: issuing the suspend command does not change the read mode of the device. the device will be in read status register mode from when the erase or program command was first issued, unless the read mode was changed prior to issuing the suspend command. not all commands are allowed when the device is suspended. ta b l e 1 0 shows which device commands are allowed during program suspend or erase suspend. during suspend, array-read operations are not allowed in blocks being erased or programmed. a block-erase under program-suspend is no t allowed. however, word-program under erase-suspend is allowed, and can be suspen ded. this results in a simultaneous erase- suspend/ program-suspend condition, indicated by sr[7,6,2] = 1. to resume a suspended program or erase operation, issue the resume command to any device address. the read mode of the device is automatically changed to read status register. the operation continues where it left off, sts (in ry/by# mode) goes low, and the respective status register bits are cleared. when the resume command is issued during a simultaneous erase-suspend/ program- suspend condition, the programming operation is resumed first. upon completion of the programming operation, the status register should be checked for any errors, and cleared. the resume command must be issued again to complete the erase operation. upon completion of the erase operation, the status register should be checked for any errors, and cleared. table 10: valid commands during suspend device command program suspend erase suspend sts configuration allowed allowed read array allowed allowed read status register allowed allowed clear status register allowed allowed read device information allowed allowed cfi query allowed allowed word/byte program not allowed allowed buffered program not allowed allowed block erase not allowed not allowed program suspend not allowed allowed erase suspend not allowed not allowed program/erase resume allowed allowed lock block not allowed not allowed unlock block not allowed not allowed program otp register not allowed not allowed
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 28 319942-02 10.0 security j3-65nm device offer both hardware and software security features. block lock operations, prs and vpen allow users to implement various levels of data protection. 10.1 normal block locking j3-65nm has the unique capability of flexible block locking (locked blocks remain locked upon reset or power cycle): all blocks are unlocked at numonyx factory. blocks can be locked individually by issuing the set block lock bit command sequence to any address within a block. once locked, blocks remain locked when power is removed, or when the device is reset (see figure 20, ?block lock operations flowchart? on page 60 ). all locked blocks are unlocked simultaneous ly by issuing the clear block lock bits command sequence to any device address. locked blocks cannot be erased or programmed. ta b l e 8 summarizes the command bus-cycles. after issuing the set block lock bit setup command or clear block lock bits setup command, the device?s read mode is automatically changed to read status register mode. after issuing the confirm command, comp letion of the operation is indicated by sts (in ry/by# mode) going high and sr.7 = 1. blocks cannot be locked or unlocked while programming or erasing, or while the device is suspended. reliable block lock and unlock operations occur only when v cc and v pen are valid. when v pen v penlk , block lock-bits cannot be changed. when the set lock-bit operation is complete , sr.4 should be checked for any error. when the clear lock-bit operation is comple te, sr.5 should be checked for any error. errors bits must be cleared using the clear status register command. block lock-bit status can be determined by first issuing the read device information command, and then reading from + 02h. dq0 indicates the lock status of the addressed block (0 = unlocked, 1 = locked). 10.2 configurable block locking one of the unique new features on the j3-65nm,which did not exist on the previous generations of this product family, is the ability to protect and/or secure the user?s system by offering multiple level of securi ties: non-volatile temporary; non-volatile semi-permanent or non-volatile permanent. for additional information and collateral request, please contact your filed representative .
december 2008 datasheet 319942-02 29 numonyx? strataflash ? embedded memory (j3-65nm) 10.3 vpen protection when it?s necessary to protect the entire array, global protection can be achieved using a hardware mechanism using vpen. whenever a valid voltage is present on vpen, blocks within the main flash array can be erased or programmed. by grounding vpen, blocks within the main array cannot be altered ? attempts to program or erase blocks will fail resulting in the setting of the appropriate error bit in the status register. by holding vpen low, absolute write protection of all blocks in the array can be achieved. 10.4 password access password access is a security enhancement offered on the j3-65nm device. this feature protects information stored in main-a rray memory blocks by preventing content alteration or reads, until a valid 64-bit password is received. password access may be combined with non-volatile protection and/or volatile protection to create a multi- tiered solution. please contact your numonyx sales for further details concerning password access.
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 30 319942-02 11.0 registers 11.1 status register the status register (sr) is an 8-bit, read-only register that indicates device status and operation errors. to read the status register, issue the read status register command. subsequent reads output status register information on dq[7:0], and 00h on dq[15:8]. sr status bits are set and cleared by the device. sr error bits are set by the device, but must be cleared using the clear status regi ster command. upon power-up or exit from reset, the status register defaults to 80h. page-mode reads are not supported in this read mode. status register contents are latched on the falling edge of oe# or the first edge of cex that enables the device. oe# must toggle to v ih or the device must be disabled before further reads to update th e status register latch. the read status register command functions independently of v pen voltage. ta b l e 1 1 shows status register bit definitions. table 11: status register description status register (sr) default value = 0x80 device write status erase suspend status erase status program status prog/erase voltage error program suspend status block-locked status reserved dws ess es ps peve pss bls 7 6 5 43210 bit name description 7 device write status (dws) 0 = device is busy; program or erase cycle in progress. 1 = device is ready; sr[6:1] are valid. 6 erase suspend status (ess) 0 = erase suspend not in effect. 1 = erase suspend in effect. 5 erase status (es) 0 = erase successful. 1 = erase fail or program sequence error when set with sr.4,sr.7. 4 program status (ps) 0 = program successful. 1 = program fail or program sequence error when set with sr.5,sr.7 3 prog/erase voltage error (peve) 0 = vpen within acceptable limits during program or erase operation. 1 = vpen v penlk during program or erase operation. 2 program suspend status (pss) 0 = program suspend not in effect. 1 = program suspend in effect. 1 block-locked status (bls) 0 = block not locked during program or erase. 1 = block locked during program or erase; operation aborted. 0 reserved 0 = default note: always clear the status register prior to resuming erase op erations. it avoids status register ambiguity when issuing commands during erase suspend. if a command sequence error occurs during an erase-suspend state, the status register contains the command sequence error status (sr[7,5,4] set). when the erase operation resumes and finishes, possible errors during the erase operation cannot be detected via the status register because it contains the previous error status
december 2008 datasheet 319942-02 31 numonyx? strataflash ? embedded memory (j3-65nm) 11.1.1 clearing th e status register the clear status register command clears the status register. it functions independent of vpen. the wsm sets and clears sr[7,6,2], but it sets bits sr[5:3,1] without clearing them. the status register should be cleared before starting a command sequence to avoid any ambiguity. a device reset also clears the status register. 11.2 status signal the status (sts) signal can be configur ed to different states using the sts configuration command ( ta b l e 1 2 ). once the sts signal has been configured, it remains in that configuration until another co nfiguration command is issued or rp# is asserted low. initially, the sts signal defa ults to ry/by# operation where ry/by# low indicates that the wsm is busy. ry/by# high indicates that the state machine is ready for a new operation or suspended. ta b l e 1 2 displays possible sts configurations. to reconfigure the status (sts) signal to other modes, the configuration command is given followed by the desired configuration co de. the three alternate configurations are all pulse mode for use as a system interrupt as described in the following paragraphs. for these configurations, bit 0 controls er ase complete interrupt pulse, and bit 1 controls program complete interrupt pulse. supplying the 00h configuration code with the configuration command resets the sts signal to the default ry/by# level mode. the configuration command may only be gi ven when the device is not busy or suspended. check sr.7 for device status. an invalid configuration code will result in sr.4 and sr.5 being set. note: sts pulse mode is not supported in the clear lock bits and set lock bit commands.
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 32 319942-02 11.3 otp protection register j3-65nm includes a 128-bit protection register (pr) that can be used to increase the security of a system design. for example, the number contained in the pr can be used to ?match? the flash component with other system components such as the cpu or asic, hence preventing device substitution. the 128-bits of the pr are divided into two 64-bit segments: ? one segment is programmed at the numonyx factory with a unique unalterable 64- bit number. ? the other segment is left blank for customer designers to program as desired. once the customer segment is programmed, it can be locked to prevent further programming. 11.3.1 reading the otp protection register the protection register is read in identification read mode. the device is switched to this mode by issuing the read identifier command (0090h). once in this mode, read cycles from addresses shown in table 13, ?word-wide protection register addressing? or table 14, ?byte-wide protection register addressing? retrieve the specified information. to return to read array mode, write the read array command (00ffh). 11.3.2 programming the ot p protection register pr bits are programmed using the two-cycle protection program command. the 64-bit number is programmed 16 bits at a time for word-wide configuration and eight bits at a time for byte-wide configuration. first wr ite the protection program setup command, 00c0h. the next write to the device will latch in address and data and program the specified location. the allowable addresses are shown in table 13, ?word-wide table 12: sts configuration coding definitions d7 d6 d5 d4 d3 d2 d1 d0 reserved 3 pulse on program complete (1) pulse on erase complete (1) d[1:0] = sts configuration codes notes 00 = default, level mode; device ready indication controls hold to a memory controller to prevent accessing a flash memory subsystem while any flash device's wsm is busy. 01 = pulse on erase complete generates a system interrupt pulse when any flash device in an array has completed a block erase. help ful for reformatting blocks after file system free space reclamation or ?cleanup.? 10 = pulse on program complete generate a system interrupt pulse when any flash device in an array has complete a program operation. provides highest performance for servicing continuous buffer write operations. 11 = pulse on erase or program complete generates system interrupts to trigger servicing of flash arrays when either erase or program operations are completed, when a common interrupt service routine is desired. notes: 1. when configured in one of the pulse modes, st s pulses low with a typical pulse width of 500 ns. 2. an invalid configuration code will resu lt in both sr.4 and sr.5 being set. 3. reserved bits are inva lid should be ignored.
december 2008 datasheet 319942-02 33 numonyx? strataflash ? embedded memory (j3-65nm) protection register addressing? on page 33 or table 14, ?byte-wide protection register addressing? on page 34 . see figure 22, ?otp register programming flowchart? on page 62 . any attempt to address protection pr ogram commands outside the defined pr address space will result in a status register error (sr.4 will be set). attempting to program a locked pr segment will result in a status register error (sr.4 and sr.1 will be set). 11.3.3 locking the otp protection register the user-programmable segment of the pr is lockable by programming bit 1 of the protection lock register (plr) to 0. bit 0 of this location is programmed to 0 at the numonyx factory to protect the unique device number. bit 1 is set using the protection program command to program ?0xfffd? to the plr. after these bits have been programmed, no further changes can be made to the values stored in the protection register. protection program commands to a locked section will result in a status register error (sr.4 and sr.1 will be set). the pr lockout state is not reversible. note: a0 is not used in x16 mode when accessing the protection register map. see ta b l e 1 3 for x16 addressing. in x8 mode a0 is used, see ta b l e 1 4 for x8 addressing. figure 6: protection register memory map table 13: word-wide protecti on register addressing word use a8a7a6a5a4a3a2a1 lock both 10000000 0 factory 10000001 1 factory 10000010 2 factory 10000011 3 factory 10000100 4 user 10000101 5 user 10000110 6 user 10000111 7 user 10001000 note: all address lines not specified in the above table must be 0 when accessing the protection register (i.e., a[max:9] = 0.) 0x88 0x85 64-bit segment (user-programmable) 0x84 0x81 0x80 lock register 0 64-bit segment (factory-programmed) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-bit protection register 0 word address a[23:1]: 128 mbit a[21:1]: 32 mbit a[22:1]: 64 mbit a[24:1]: 256 mbit
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 34 319942-02 table 14: byte-wide protection register addressing byteusea8a7a6a5a4a3a2a1a0 lockboth100000000 lockboth100000001 0factory100000010 1factory100000011 2factory100000100 3factory100000101 4factory100000110 5factory100000111 6factory100001000 7factory100001001 8user100001010 9user100001011 auser100001100 buser100001101 cuser100001110 duser100001111 euser100010000 fuser100010001 note: all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a[max:9] = 0.
december 2008 datasheet 319942-02 35 numonyx? strataflash ? embedded memory (j3-65nm) 12.0 power and reset specifications 12.1 power-up and power-down power supply sequencing is not required if vpen is connected to vcc or vccq. otherwise vcc and vccq should attain their minimum operating voltage before applying vpen. power supply transitions should only occur when rp# is low. this protects the device from accidental programming or erasure during power transitions. 12.1.1 power-up/down characteristics to prevent conditions that could result in spurious program or erase operations, several valid power-up/power-down sequences shown in ta b l e 1 5 are recommended. for dc voltage characteristics refer to ta b l e 2 0 . note that each power supply must reach its minimum voltage range before applying/removing the next supply voltage. note: power supplies connected or sequenced together. device inputs must not be driven until all supply voltages reach their minimum range. rp# should be low during power transitions. table 15: power-up/down sequence power supply voltage power-up sequence power-down sequence v cc(min) 1st 1st 1st ? sequencing not required ? 3rd 2nd 2nd ? sequencing not required ? v ccq(min) 2nd 2nd ? 2nd 1st ? v pen(min) 3rd 2nd 1st 1st
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 36 319942-02 12.2 reset specifications asserting rp# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. if a cpu reset occu rs without a flash memory rese t, proper cpu initialization may not occur. this is because the flash me mory may be providing status information, instead of array data as expected. connect rp# to the same active low reset signal used for cpu initialization. also, because the device is disabled when rp# is asserted, it ignores its control inputs during power-up/down. invalid bus conditions are masked, providing a level of memory protection. table 16: power and reset num symbol parameter min max unit notes p1 t plph rp# pulse width low 100 - ns 1,2,3,4 p2 t plrh rp# low to device re set during erase - 25 s 1,3,4,7 rp# low to device reset during program - 25 1,3,4,7 p3 t vccph vcc power valid to rp# de-assertion (high) 300 - 1,4,5,6 notes: 1. these specifications are valid for all device versions (packages and speeds). 2. the device may reset if t plph is < t plph min, but this is not guaranteed. 3. not applicable if rp# is tied to vcc. 4. sampled, but not 100% tested. 5. when rp# is tied to the vcc supp ly, device will not be ready until t vccph after vcc v ccmin . 6. when rp# is tied to the vccq su pply, device will no t be ready until t vccph after vcc v ccmin . 7. reset completes within t plph if rp# is asserted while no eras e or program operation is executing. figure 7: reset operation waveforms ( a) reset during read mode (b) reset during program or block erase p1 p2 (c) reset during program or block erase p1 p2 v ih v il v ih v il v ih v il rst# [p] rst# [p] rst# [p] abort complete abort complete v cc 0v v cc (d) vcc power-up to rst# high p1 r5 p2 p3 p2 r5 r5
december 2008 datasheet 319942-02 37 numonyx? strataflash ? embedded memory (j3-65nm) 12.3 power supply decoupling flash memory devices require careful power supply de-coupling. three basic power supply current considerations are: 1) standb y current levels; 2) active current levels; and 3) transient peaks produced when ce x and oe# are asserted and deasserted. when the device is accessed, many internal conditions change. circuits within the device enable charge-pumps, and internal lo gic states change at high speed. all of these internal activities produce transient si gnals. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. because numonyx mlc flash memory devices draw their power from vcc, vss, and vccq, each power connection should have a 0.1 f ceramic capacitor to ground. high- frequency, inherently low-inductance capacito rs should be placed as close as possible to package leads. additionally, for every eight devices used in the system, a 4.7 f electrolytic capacitor should be placed between power and ground cl ose to the devices. the bulk capacitor is meant to overcome voltage droop caused by pcb trace inductance.
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 38 319942-02 13.0 maximum ratings and operating conditions 13.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. 13.2 operating conditions warning: operation beyond the ?operating condit ions? is not recommended and extended exposure beyond the ?operating cond itions? may affect device reliability notice: this document contains information available at the time of its release. the specifications are subject to change witho ut notice. verify with your local numonyx sales office that you have the latest datasheet before finalizing a design. table 17: absolute maximum ratings parameter min max unit notes temperature under bias expanded (t a , ambient) ?40 +85 c ? storage temperature ?65 +125 c ? v cc & v ccq voltage ?2.0 +5.6 v 2 voltage on any input/output signal (except vcc, vccq) ?2.0 v ccq (max) + 2.0 v 1 i sh output short circuit current ? 100 ma 3 notes: 1. voltage is referenced to v ss . during infrequent non-periodic transitions, the voltage potential between v ss and input/ output pins may undershoot to ?2.0 v for periods < 20 ns or overshoot to v ccq (max) + 2.0 v for periods < 20 ns. 2. during infrequent non-periodic transitions, the voltage potential between v cc and the supplies may undershoot to ?2.0 v for periods < 20 ns or v supply (max) + 2.0 v for periods < 20 ns. 3. output shorted must be no more than one second. no more than one output can be shorted at a time. table 18: temperature and v cc operating condition symbol parameter min max unit test condition t a operating temperature (amibent )-40 +85 cambient temperature v cc v cc supply voltage 2.7 3.6 v ? v ccq i/o supply voltage 2.7 3.6 v ? block erase cycles main blocks 100k ? cycles ?
december 2008 datasheet 319942-02 39 numonyx? strataflash ? embedded memory (j3-65nm) 14.0 electrical characteristics 14.1 dc current specifications please refer to figure 6, ?chip enable truth table for 256-mb? on page 15 to understand the device is disable or enabled. table 19: dc current characteristics symbol parameter density 2.7 - 3.6v test conditions notes typ max unit i li input and v pen load current ? 1 a v cc = v ccmax v ccq = v ccqmax v in = v ccq or v ss 1 i lo output leakage current ? 1 i ccs, i ccd v cc standby current, v cc power-down current 256-mbit 65 210 a v cc = v ccmax v ccq = v ccqmax ce# = v ccq rp# = v ccq (for i ccs ) rp# = v ss (for i ccd ) 1,2,3 i ccr v cc page mode read current single word 26 31 ma v cc = v ccmax ce# = v il oe# = v ih inputs: v ih or v il f = 5mhz (1 clk) 1 page 12 16 ma v cc = v ccmax ce# = v il oe# = v ih inputs: v ih or v il f = 13mhz (17 clk) i ccw, i cce v cc program, v cc erase 35 50 ma v pen = v penh , program/erase in progress 1,3 i ccws i cces v cc program suspend v cc erase suspend refer to i ccs ace# = v ccq , suspend in progress 1,4 notes: 1. all currents are in rms unle ss otherwise noted. these currents are valid for all product vers ions (packages and speeds). 2. includes sts. 3. sampled, not 100% tested. 4. i ccws and i cces are specified with the device selected. if the de vice is read or written while in erase suspend mode, the device?s current draw is i ccr and i ccws .
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 40 319942-02 14.2 dc voltage specifications 14.3 capacitance table 20: dc voltage characteristics symbol parameter 2.7 - 3.6 v test conditions notes min max unit v il input low voltage ?0.5 0.6 v 2, 5, 6 v ih input high voltage 2.0 v ccq + 0.5v v2, 5, 6 v ol output low voltage ?0.4v v cc = v cc min v ccq = v ccq min i ol = 2 ma 1, 2 ?0.2v v cc = v cc min v ccq = v ccq min i ol = 100 a v oh output high voltage 0.85 v ccq ?v v cc = v ccmin v ccq = v ccq min i oh = ?2.5 ma 1, 2 v ccq ? 0.2 ?v v cc = v ccmin v ccq = v ccq min i oh = ?100 a v penlk v pen lockout during program, erase and lock-bit operations ?2.2v 2, 3 v penh v pen during block erase, program, or lock-bit operations 2.7 3.6 v 3 v lko v cc lockout voltage 1.5 ? v 4 v lkoq v ccq lockout voltage 0.9 ? v notes: 1. includes sts. 2. sampled, not 100% tested. 3. block erases, programming, and lock-bit configurations are inhibited when v pen v penlk , and not guaranteed in the range between v penlk (max) and v penh (min), and above v penh (max). 4. block erases, programming, and lock-bit configurations are inhibited when v cc < v lko , and not guaranteed in the range between v lko (min) and v cc (min), and above v cc (max). 5. includes all operational modes of the device including standby and power-up sequences 6. input/output signals can undershoot to -1.0v referenced to v ss and can overshoot to v ccq + 1.0v for duration of 2ns or less, the v ccq valid range is referenced to v ss . table 21: capacitance symbol parameter signals min typ max unit condition note c in input capacitance address, data, ce#, we#, oe#, byte#,rp# 26 7 pf typ temp = 25 c, max temp = 85 c, vcc = (0 v - 3.6 v), vccq = (0 v - 3.6 v), discrete silicon die 1,2,3 c out output capacitance data, sts 2 4 5 pf notes: 1. capacitance values are for a single die. 2. sampled, not 100% tested. 3. silicon die capacita nce only, add 1 pf for discrete packages.
december 2008 datasheet 319942-02 41 numonyx? strataflash ? embedded memory (j3-65nm) 15.0 ac characteristics timing symbols used in the timing diagrams within this document conform to the following convention note: exceptions to this convention include t acc and t apa . t acc is a generic timing symbol that refers to the aggregate initial-access delay as determined by t avqv , t elqv , and t glqv (whichever is satisfied last) of the flash device. t apa is specified in the flash device?s data sheet, and is the address-to-data delay for subsequent page-mode reads. 15.1 ac test conditions note: ac test inputs are driven at vccq for logic "1" and 0 v fo r logic "0." input/output timing begins/ends at vccq/2. input rise and fall times (10% to 90%) < 5 ns. worst-case speed occurs at vcc = vccmin. figure 8: timing signal naming convention figure 9: timing signal name decoder signal code state code address a high h data - read q low l data - write d high-z z chip enable (ce) e low-z x output enable (oe#) g valid v write enable (we#) w invalid i byte# f reset (rp#) p sts r vpen v e t l q v source signal target state source state target signal figure 10: ac input/outp ut reference waveform io_ref.wmf input v ccq /2 v ccq /2 output v ccq 0v test points
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 42 319942-02 notes: 1. see the following table for component values. 2. test configuration component value for worst case speed conditions. 3. c l includes jig capacitance . figure 11: transient equivalent testing load circuit table 22: test configuration component value for worst case speed conditions test configuration c l (pf) vccq min standard test 30 device under test out c l
december 2008 datasheet 319942-02 43 numonyx? strataflash ? embedded memory (j3-65nm) 15.2 ac read specifications chip enable truth table can be found on table 6 on page 15 test configuration can be found in table 22 on page 42 notes: 1. ce x low is defined as the falling edge of ce0, ce1, or ce2 that enables the device. ce x high is defined as the rising edge of ce0, ce1, or ce2 that disables the device 2. see ac input/output reference waveforms for the maximum allowable input slew rate. 3. oe# may be delayed up to t elqv -t glqv after the falling edge of ce0, ce1, or ce2 that enables th e device without impact on t elqv . 4. sampled, not 100% tested. 5. for devices configured to standard word/byte read mode, r15 (t apa ) will equal r2 (t avqv ). table 23: ac read specification nbr. symbol parameter package min max unit notes r1 t avav read/write cycle time easy bga 95 ? ns 1,2,3 tsop 105 ? r2 t avqv address to output delay easy bga ? 95 ns 1,2,3 tsop ? 105 r3 t elqv ce x to output delay easy bga ? 95 ns 1,2,3 tsop ? 105 r4 t glqv oe# to non-array output delay ? 25 ns 1,2,3 r5 t phqv rp# high to output delay ? 150 ns 1,2,3 r6 t elqx ce x to output in low z 0 ? ns 1,2,3,4 r7 t glqx oe# to output in low z 0 ? ns 1,2,3,4 r8 t ehqz ce x high to output in high z ? 20 ns 1,2,3,4 r9 t ghqz oe# high to output in high z ? 15 ns 1,2,3,4 r10 t oh output hold from address, ce x , or oe# change, whichever occurs first 0 ? ns 1,2,3,4 r11 t elfl/ t elfh ce x low to byte# high or low ? 10 ns 1,2,3,4 r12 t flqv/ t fhqv byte# to output delay ? 1 s 1,2,3 r13 t flqz byte# to output in high z ? 1 s 1,2,3,4 r14 t ehel cex high to cex low 0 ? ns 1,2,3,4 r15 t apa page address access time ? 25 ns 4, 5 r16 t glqv oe# to array output delay ? 25 ns 1,2,3
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 44 319942-02 notes: 1. ce x low is defined as the falling edge of ce0, ce1, or ce2 that enables the device. ce x high is defined as the rising edge of ce0, ce1, or ce2 that disables the device. 2. when reading the flash array a faster t glqv (r16) applies. for non-array reads, r4 applies (i.e., status register reads, query reads, or device identifier reads). note: 1. ce x low is defined as the falling edge of ce0, ce1, or ce2 that enables the device. ce x high is defined as the rising edge of ce0, ce1, or ce2 that disables the device. 2. in this diagram, byte# is asserted high. figure 12: single word as ynchronous read waveform r11 r5 r12 r13 r10 r4 r16 r7 r6 r9 r8 r3 r1 r2 r1 a ddress [a] cex [e] oe# [g] we# [w] data [d/q] byte#[f] rp# [p] figure 13: 4-word asynchronous page mode read waveform 00 01 10 11 1 2 3 4 r10 r15 r10 r5 r9 r8 r7 r6 r4 r3 r1 r2 r1 a [max:3] [a] a[2:1] [a] cex [e] oe# [g] we# [w] d[15:0] [q] rp# [p]
december 2008 datasheet 319942-02 45 numonyx? strataflash ? embedded memory (j3-65nm) notes: 1. ce x low is defined as the falling edge of ce0, ce1, or ce2 that enables the device. ce x high is defined at the rising edge of ce0, ce1, or ce2 that disables the device. 2. in this diagram, byte# is asserted high. figure 14: 16-word asynch ronous page mode read a[max:5][a] 1 2 16 15 r2 r1 r3 r4 r7 r6 r5 r10 r15 r10 r9 r8 a[4:1][a] cex[e] oe#[g] we#[w] dq[15:0][q] rp#[p] byte#
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 46 319942-02 15.3 ac write specification ce x low is defined as the falling edge of ce0, ce1, or ce2 that enables the device. ce x high is defined at the rising edge of ce0, ce1, or ce2 that disables the device. chip enable truth table can be found in table 6 on page 15 table 24: ac write specification nbr. symbol parameter min max unit notes w1 t phwl (t phel ) rp# high recovery to we# (ce x ) going low 150 ? ns 1,2,3 w2 t elwl (t wlel )ce x (we#) low to we# (ce x ) going low 0 ? ns 1,2,4 w3 t wp write pulse width 50 ? ns 1,2,4 w4 t dvwh (t dveh ) data setup to we# (ce x ) going high 50 ? ns 1,2 w5 t avwh (t aveh )address setup to we# (ce x ) going high 50 ? ns 1,2 w6 t wheh (t ehwh )ce x (we#) hold from we# (ce x ) high 0 ? ns 1,2, w7 t whdx (t ehdx ) data hold from we# (ce x ) high 0 ? ns 1,2, w8 t whax (t ehax ) address hold from we# (ce x ) high 0 ? ns 1,2, w9 t wph write pulse width high 20 ? ns 1,2,5 w11 t vpwh (t vpeh )v pen setup to we# (ce x ) going high 0 ? ns 1,2,3 w14 t whgl (t ehgl ) write recovery before read 0 ? ns 1,2,6 w13 t whrl (t ehrl )we# (ce x ) high to sts going low ? 500 ns 1,2,7 w15 t qvvl v pen hold from valid srd, sts going high 0 ? ns 1,2,3,7,8 notes: 1. read timing characteristics during block erase, program, an d lock-bit configuration operations are the same as during read-only operations. refer to ac characteristics?read-only operations . 2. a write operation can be initiate d and terminated with either ce x or we#. 3. sampled, not 100% tested. 4. write pulse width (t wp ) is defined from ce x or we# going low (whichever goes low last) to ce x or we# going high (whichever goes high first). hence, t wp = t wlwh = t eleh = t wleh = t elwh . 5. write pulse width high (t wph ) is defined from ce x or we# going high (whichever goes high first) to ce x or we# going low (whichever goes low first). hence, t wph = t whwl = t ehel = t whel = t ehwl . 6. for array access, t avqv is required in addition to t whgl for any accesses after a write. 7. sts timings are based on sts configured in its ry/by# default mode. 8. v pen should be held at v penh until determination of block erase, program, or lock-bit configuration success (sr[5:3,1] = 0).
december 2008 datasheet 319942-02 47 numonyx? strataflash ? embedded memory (j3-65nm) figure 15: asynchron ous write waveform d w11 w1 w13 w7 w4 w9 w9 w3 w3 w2 w6 w8 w5 address [a] cex (we# ) [e (w)] we# (cex) [w (e)] oe# [g] data [d/q] sts[r] rp# [p] vpen [v] figure 16: asynchronous write to read waveform d w11 w1 w7 w4 w14 w3w3 w2 w6 w8 w5 address [a] ce# [e] we# [w] oe# [g] data [d/q] rst#/ rp# [p] vpen [v]
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 48 319942-02 16.0 program and erase characteristics 16.1 program & erase specifications typical values measured at t a = +25 c and nominal voltages table 25: program-erase characteristics nbr. symbol parameter typ max (8) unit notes conventional word programming w200 t prog/w single word main array 150 456 s buffered programming w250 t prog/b aligned 32-word bp time (64 bytes) 176 716 s aligned 64-word bp time (128 bytes) 216 900 aligned 128-word bp time (256 bytes) 272 1140 aligned 256-word bp time 396 1690 1 one full buffer(512-word) 700 3016 1 erasing and suspending w501 t ers/mb erase time for 64-kw main array block 0.8 4 s w602 t ers/susp erase or erase-resume command to erase-suspend command ? 500 s w600 t susp/p program suspend time 20 25 s w601 t susp/e erase suspend time 20 25 notes: 1. does not apply when in byte mode (byte# at vil)
december 2008 datasheet 319942-02 49 numonyx? strataflash ? embedded memory (j3-65nm) 17.0 ordering information figure 17: part number decoder l lithography f = 65 nm product family j3 = numonyx tm strataflash ? embedded memory j3 v cc = 3v v ccq = 3v p c 2 8 f 2 5 6 j 3 f 1 0 5 access speed 95 ns 105 ns device density package te= 56-lead tsop js = pb-free 56-tsop rc = 64-ball easy bga pc = 64-ball pb-free easy bga product line designator 28f = numonyx tm flash memory 256 = x8/x16 (256 mbit) table 26: valid combinations 256-mbit te28f256j3f105 js28f256j3f105 pc28f256j3f95 rc28f256j3f95
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 50 319942-02 appendix a reference information a.1 common flash interface the cfi specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. this allows device independent, jedec id-independent, and forward- and backward-compatible software support for the specified flash device families. it allows flash vendors to standardize their existing interfaces for long-term compatibility. this section defines the data structure or ?database? returned by the cfi query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. the query is part of an overall specification for multiple comm and set and control interface descriptions called cfi. a.2 query structure output the query ?database? allows system software to gain information for controlling the flash component. this section describes the de vice?s cfi-compliant interface that allows the host system to access query data. query data are always presented on the lo west-order data outputs (d[7:0]) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two bytes of the query structure, ?q? and ?r? in ascii, appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. th us, the device outputs ascii ?q? in the low byte (d[7:0]) and 00h in the high byte (d[15:8]). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower addre ss, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the ?h? suffix has been dropped. in addition, since the upper byte of word- wide devices is always ?00h,? the leadin g ?00? has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. table 27: summary of query structure outp ut as a function of device and mode device type/ mode query start location in maximum device bus width addresses query data with maximum device bus width addressing query data with byte addressing hex offset hex code ascii value hex offset hex code ascii value x16 device 10h 10: 0051 ?q? 20: 51 ?q? x16 mode 11: 0052 ?r? 21: 00 ?null? 12: 0059 ?y? 22: 52 ?r? x16 device 20: 51 ?q?
december 2008 datasheet 319942-02 51 numonyx? strataflash ? embedded memory (j3-65nm) a.2.1 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or ?databas e.? the structure sub-sections and address locations are summarized below. see ap-646 common flash interface (cfi) and command sets (order number 292204) for a full description of cfi. the following sections describe the query structure sub-sections in detail. x8 mode n/a (1) n/a (1) 21: 51 ?q? 22: 52 ?r? note: 1. the system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. therefore, word addressing, where these lower addresses are not toggled by the system, is "not applicable" for x8-configured devices. table 28: example of query structure ou tput of a x16- and x8-capable device word addressing byte addressing offset hex code value offset hex code value a 15 ?a 0 d15?d 0 a 7 ?a 0 d 7 ?d 0 0010h 0051 ?q? 20h 51 ?q? 0011h 0052 ?r? 21h 51 ?q? 0012h 0059 ?y? 22h 52 ?r? 0013h p_id lo prvendor 23h 52 ?r? 0014h p_id hi id # 24h 59 ?y? 0015h p lo prvendor 25h 59 ?y? 0016h p hi tbladr 26h p_id lo prvendor 0017h a_id lo altvendor 27h p_id lo prvendor 0018h a_id hi id # 28h p_id hi id # ... ... ... ... ... ... table 27: summary of query structure outp ut as a function of device and mode device type/ mode query start location in maximum device bus width addresses query data with maximum device bus width addressing query data with byte addressing hex offset hex code ascii value hex offset hex code ascii value table 29: query structure offset sub-section name description notes 00h manufacturer code 1 01h device code 1 (ba+2)h (2) block status register block-specific information 1,2 04-0fh reserved reserved for vendor-specific information 1 10h cfi query identification string rese rved for vendor-specific information 1 1bh system interface information command set id and vendor data offset 1
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 52 319942-02 a.2.2 block status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. a.2.3 cfi query identification string the cfi query identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). 27h device geometry definition flash device layout 1 p (3) primary numonyx-sp ecific extended query table vendor-defined additional information specific to the primary vendor algorithm 1,3 notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 02000h is block 2?s beginning location when the block size is 128 kbyte). 3. offset 15 defines ?p? which points to the primary numonyx-specific extended query ta b l e . table 29: query structure offset sub-section name description notes table 30: block status register offset length description address value (ba+2)h (1) 1 block lock status register ba+2: --00 or --01 bsr.0 block lock status 0 = unlocked 1 = locked ba+2: (bit 0): 0 or 1 bsr 2?7: reserved for future use ba+2: (bit 2-7): 0 note: 1. ba = the beginning location of a block address (i.e., 008000h is block 1?s (64-kb block) beginning location in word mode). table 31: cfi identification offset length description add. hex code value 10h 3 query-unique ascii string ?qry? 10 --51 ?q? 11: --52 ?r? 12: --59 ?y? 13h 2 primary vendor command set and control interface id code. 13: --01 16-bit id code for vendor-specified algorithms 14: --00 15h 2 extended query table primary algorithm address 15: --31 16: --00 17h 2 alternate vendor command set and control interface id code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00
december 2008 datasheet 319942-02 53 numonyx? strataflash ? embedded memory (j3-65nm) a.2.4 system interf ace information the following device information can optimize system interface software. a.2.5 device geometry definition this field provides critical details of the flash device geometry. table 32: system interface information offset length description add. hex code value 1bh 1 v cc logic supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1b: --27 2.7 v 1ch 1 v cc logic supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1c: --36 3.6 v 1dh 1 v pen [programming] supply mini mum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1d: --00 0.0 v 1eh 1 v pen [programming] supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1e: --00 0.0 v 1fh 1 ?n? such that typical single word program time-out = 2 n s 1f: --08 256 s 20h 1 ?n? such that typical ma x. buffer write time-out = 2 n s 20: --0a 1024 s 21h 1 ?n? such that typical block erase time-out = 2 n ms 21: --0a 1 s 22h 1 ?n? such that typical full chip erase time-out = 2 n ms 22: --00 na 23h 1 ?n? such that maximum word program time-out = 2 n times typical 23: --01 512 s 24h 1 ?n? such that maximum buffer write time-out = 2 n times typical 24: --02 4096 s 25h 1 ?n? such that maximum block erase time-out = 2 n times typical 25: --02 4 s 26h 1 ?n? such that maximum chip erase time-out = 2 n times typical 26: --00 na table 33: device geometry definition offset length description code see table below 27h 1 ?n? such that device size = 2 n in number of bytes 27: 28h 2 flash device interface: x8 async x16 async x8/x16 async 28: --02 x8/ x16 28:00,29:00 28:01,29:00 28:02,29:00 29: --00 2ah 2 ?n? such that maximum number of bytes in write buffer = 2 n 2a: --0a 1024 bytes 2b: --00 2ch 1 number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in ?bulk? 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks 3. symmetrically blocked partitions have one blocking region 4. partition size = (total blocks) x (individual block size) 2c: --01 1 2dh 4 erase block region 1 information 2d: bits 0?15 = y, y+1 = number of identical-size erase blocks 2e: bits 16?31 = z, region erase block(s) size are z x 256 bytes 2f: 30:
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 54 319942-02 a.2.6 primary-vendor specific extended query table certain flash features and commands are optional. the primary vendor-specific extended query table specifies this and other similar information. table 34: device geometry: address codes address 256 mbit 27: --19 28: --02 29: --00 2a: --05 2b: --00 2c: --01 2d: --ff 2e: --00 2f: --00 30: --02 table 35: primary vendor-specific extended query (sheet 1 of 2) offset (1) p = 31h length description (optional flash features and commands) add. hex code value (p+0)h 3 primary extended query table 31: --50 ?p? (p+1)h unique ascii string ?pri? 32: --52 ?r? (p+2)h 33: --49 ?i? (p+3)h 1 major version number, ascii 34: --31 ?1? (p+4)h 1 minor version number, ascii 35: --31 ?1? (p+5)h (p+6)h (p+7)h (p+8)h 4 optional feature and command support (1=yes, 0=no) undefined bits are ?0.? if bit 31 is ?1? then another 31 bit field of optional features follows at the end of the bit-30 field. 36: --ce 37: --00 38: --00 39: --00 bit 0 chip erase supported bit 0 = 0 no bit 1 suspend erase supported bit 1 = 1 yes bit 2 suspend program supported bit 2 = 1 yes bit 3 legacy lock/unlock supported bit 3 = 1 (1) yes (1) bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 0 no bit 6 protection bits supported bit 6 = 1 yes bit 7 page-mode read supported bit 7 = 1 yes bit 8 synchronous read supported bit 8 = 0 no bit9 simultaneous operat ion supported bit 9 = 0 no bit 30 cfi link(s) to follow (256 mb) bit 30 = 0 no bit 31 another ?optional feature? field to follow bit 31 = 0 no
december 2008 datasheet 319942-02 55 numonyx? strataflash ? embedded memory (j3-65nm) (p+9)h 1 supported functions after suspen d: read array, status, query other supported operations are: bits 1?7 reserved; undefined bits are ?0? 3a: --01 bit 0 program supported after erase suspend bit 0 = 1 yes (p+a)h (p+b)h 2 block status register mask 3b: --01 bits 2?15 are reserved; undefined bits are ?0? 3c: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-down bit status active bit 1 = 0 no (p+c)h 1 v cc logic supply highest performance program/erase voltage bits 0?3 bcd value in 100 mv bits 4?7 bcd value in volts 3d: --33 3.3 v (p+d)h 1 v pen optimum program/erase supply voltage bits 0?3 bcd value in 100 mv bits 4?7 hex value in volts 3e: --00 0.0 v note: 1. future devices may not support the described ?legacy lock/unlock? function. thus bit 3 would have a value of ?0.? 2. setting this bit, will lead to the extension of the cfi table. table 36: protection register information offset (1) p = 31h length description (optional flash features and commands) add. hex code value (p+e)h 1 number of protection register fields in jedec id space. ?00h,? indicates that 256 protection bytes are available 3f: --01 01 (p+f)h (p+10)h (p+11)h (p+12)h 4 protection field 1: protection description this field describes user-available one time programmable (otp) protection register bytes. some are pre-programmed with device- unique serial numbers. others are user-programmable. bits 0-15 point to the protection register lock byte, the section?s first byte. the following bytes are factory pre-programmed and user-programmable. bits 0-7 = lock/bytes jedec-plane physical low address bits 8-15 = lock/bytes jedec-plane physical high address bits 16-23 = ?n? such that 2 n = factory pre-programmed bytes bits 24-31 = ?n? such that 2 n = user-programmable bytes 40: 41: 42: 43: --80 --00 --03 --03 80h 00h 8bytes 8bytes note: 1. the variable p is a pointer whic h is defined at cfi offset 15h. table 35: primary vendor-specific extended query (sheet 2 of 2) offset (1) p = 31h length description (optional flash features and commands) add. hex code value
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 56 319942-02 table 37: burst read information offset (1) p = 31h length description (optional flash features and commands) add. hex code value (p+13)h 1 page mode read capability bits 0?7 = ?n? such that 2 n hex value represents the number of read- page bytes. see offset 28h for device word width to determine page- mode data output width. 00h indicates no read page buffer. 44: --05 32 bytes (p+14)h 1 number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. 45: --00 0 (p+15)h 1 synchronous mode read ca pability configuration 1 bits 3-7 = reserved bits 0-2 = ?n? such that 2 n+1 hex value represents the maximum number of continuous synchronous burst reads when the device is configured for its maximum word widt h. a value of 07h indicates that the device is capable of continuous linear bursts until that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bits 0-2 if the device is configured for its maximum word width. see offset 1fh for word width to determine the burst data output width. 46: --00 n/a (p+16h)h 1 synchronous mo de read capability conf iguration 2 47: --00 n/a (p+45h)h 1 j3c mark for vil fix for customers 76: --01 01 note: 1. the variable p is a pointer which is defined at cfi offset 15h.
december 2008 datasheet 319942-02 57 numonyx? strataflash ? embedded memory (j3-65nm) a.3 flow charts figure 18: program/erase suspend/resume flowchart start erase suspended ? (sr.6 = '1') read status register see status register flowchart program device see program flowchart end wait t susp error handler user-defined routine command cycle - issue suspend command - address = any device address - data = 0xb0 command cycle - issue resume command - address = any device address - data = 0xd0 yes yes yes yes yes no no no no no yes no read device program suspended ? (sr.2 = '1') program suspended ? (sr.2 = '1') any errors ? read ? program ?
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 58 319942-02
december 2008 datasheet 319942-02 59 numonyx? strataflash ? embedded memory (j3-65nm) figure 19: buffer program flowchart start get next target address issue write to buffer command e8h and block address read status register (at block address) is wsm ready? sr.7 = 1 = yes device supports buffer writes? set timeout or loop counter timeout or count expired ? write confirm d0h and block address another buffered programming? yes no no write buffer data, start address x = 0 yes 0 = n o no yes use single word programming abort bufferred program? no x = n? write buffer data, block address x = x + 1 write to another block address buffered program aborted no yes yes write word count, block address 1. word count values on dq 0 -dq 7 are loaded into the count register. count ranges for this device are n = 0000h to 0001fh. 2. the device outputs the status register when read. 3. write buffer contents will be programmed at the device start address or destination flash address. 4. align the start address on a write buffer boundary for maximum programming performance (i.e., a 4 ?a 0 of the start address = 0). 5. the device aborts the buffered program command if the current address is outside the original block address. 6. the status register indicates an "improper command sequence" if the buffered program command is aborted. follow this with a clear status register command. full status check can be done after all erase and write sequences complete. write ffh after the last operation to reset the device to read array mode. bus operation standby read co mman d write write to buffer read standby co mmen t s check sr.7 1 = wsm ready 0 = wsm busy status register data ce# and oe# low updates sr addr = block address data = e8h addr = block address sr.7 = valid addr = block address check sr.7 1 = device wsm is busy 0 = device wsm is ready write program confirm data = d0h addr = block address write (notes 1, 2) data = n-1 = word count n = 0 corresponds to count = 1 addr = block address write (notes 3, 4) data = write buffer data addr = start address write (notes 5, 6) data = write buffer data addr = block address suspend program loop read status register sr.7 =? full status check if desired program complete suspend program 1 0 no yes
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 60 319942-02 figure 20: block lock operations flowchart start command cycle - issue block lock setup command - address = block address - data = 0x60 data cycle - issue lock/unlock command - address = block address - data = 0x01 (lock block) -or- 0xd0 (unlock block) read status register see status register flowchart yes no yes done no command cycle - issue read device id command - address = block base address + 0x2 - data = 0x90 error handler user-defined routine errors ? check lock status ? data cycle - read block lock status block status d1 d0 unlocked 0 0 locked 0 1
december 2008 datasheet 319942-02 61 numonyx? strataflash ? embedded memory (j3-65nm) figure 21: block erase flowchart start confirm cycle - issue confirm command - address = block to be erased - data = erase confirm (0xd0) errors ? yes no error-handler user defined routine check ready status - read status register command not required - perform read operation - read ready status on signal sr.7 command cycle - issue erase command - address = block to be erased - data = 0x20 yes sr.7 = '1' ? end no suspend ? no yes read status register - toggle ce# or oe# to update status register - see status register flowchart erase suspend see suspend/ resume flowchart
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 62 319942-02 figure 22: otp register programming flowchart start confirm data - write otp address and data yes sr.7 = '1' ? end no read status register - toggle ce# or oe# to update status register - see status register flowchart otp program setup - write 0xc0 - otp address check ready status - read status register command not required - perform read operation - read ready status on signal sr.7
december 2008 datasheet 319942-02 63 numonyx? strataflash ? embedded memory (j3-65nm) figure 23: status register flowchart start sr7 = '1' sr2 = '1' sr4 = '1' sr3 = '1' sr1 = '1' yes yes no yes no no no sr6 = '1' yes no sr5 = '1' no no program suspend see suspend /resume flowchart erase suspend see suspend /resume flowchart error command sequence yes yes yes error erase failure error program failure error v pen/pp < v penlk/pplk error block locked -set by wsm - reset by user - see clear status register command - set/reset by wsm sr4 = '1' yes no end command cycle - issue status register command - address = any device address - data = 0x70 data cycle - read status register sr[7:0]
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 64 319942-02 appendix b terms, definitions, and acronyms b.1 nomenclature b.2 acronyms amin all densities amin = a0 for x8 all densities amin = a1 for x16 amax 256 mbit amax = a24 block a group of flash cells that share common erase circuitry and erase simultaneously. clear indicates a logic zero (0) program writes data to the flash array set indicates a logic one (1) vpen refers to a signal or package connection name v pen refers to timing or voltage levels cui command user interface otp one time programmable plr protection lock register pr protection register prd protection register data rfu reserved for future use sr status register srd status register data wsm write state machine cfi common flash interface fdi flash data integrator mlc multi-level cell sbc single bit cell nc not connect du don?t use
december 2008 datasheet 319942-02 65 numonyx? strataflash ? embedded memory (j3-65nm) b.3 conventions h: hexadecimal suffix k (noun): 1,000 m (noun): 1,000,000 bit: 1 bit nibble: 4 bits byte: 8 bits word: 16 bits kbyte: 1,024 bytes kword: 1,024 words kb: 1,024 bits kb: 1,024 bytes mb: 1,048,576 bits mb: 1,048,576 bytes brackets: square brackets ([]) will be used to designate group membership or to define a group of signals with similar function (i.e. a[21:1], sr[4,1] and d[15:0]). 00ffh: denotes 16-bit hexadecimal numbers 00ff 00ffh: denotes 32-bit hexadecimal numbers dq[15:0]: data i/o signals
numonyx? strataflash ? embedded memory (j3-65nm) datasheet december 2008 66 319942-02 appendix c revision history date revision description may 2008 01 initial release december 2008 02 for 256-mbit j3-65nm release

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